1. Technical Field
The present invention relates to integrated circuits in general, and in particular to complementary metal-oxide semiconductor (CMOS) integrated circuits. Still more particularly, the present invention relates to a CMOS level shifter circuit.
2. Description of Related Art
Quite often, integrated circuit (IC) devices manufactured under the current technology have to interface with IC devices manufactured under previous technologies. However, the CMOS voltage levels in IC devices from the current technology are usually different from the CMOS voltage levels in IC devices from previous technologies.
For example, the CMOS voltage levels in IC devices from the current technology typically range from 0 V to 1.2 V, and the CMOS voltage levels in IC devices from previous technologies typically range from 0 V to 3.3 V. Thus, in order to ensure proper interfacing between different CMOS voltage levels, IC devices manufactured under the current technology must include output buffer circuits that are capable of driving voltages greater than the core voltage.
Generally speaking, an output buffer circuit employs a level shifter circuit that is coupled to a power supply having a voltage different from the source voltage. In response to the values of the input signals, the level shifter circuit uses a set of output drivers to provide proper output voltages accordingly. For example, an output buffer circuit that receives input signals ranging from 0 V to 1.2 V output should be able to output signals ranging from 0 V to 3.3 V.
The present disclosure describes a level shifter circuit having improved characteristics in low-to-high voltage transition operations.